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1M x 16-Bit Dynamic RAM (4k-Refresh)
HYB5116160BSJ-50/-60/-70
Advanced Information
* * *
1 048 576 words by 16-bit organization 0 to 70 C operating temperature Performance: -50 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 90 35 -60 60 15 30 110 40 -70 70 20 35 130 45 ns ns ns ns ns
* *
* * * * * * *
Single + 5 V ( 10 %) supply Low power dissipation max. 550 active mW (-50 version) max. 495 active mW (-60 version) max. 440 active mW (-70 version) 11 mW standby (TTL) 5.5. mW standby (MOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and self refresh Fast page mode capability 2 CAS / 1 WE All inputs, outputs and clocks fully TTL-compatible 4096 refresh cycles/64 ms Plastic Package: P-SOJ-42-1 400 mil
Semiconductor Group
1
1.96
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
The HYB 5116160BSJ is a 16 MBit dynamic RAM organized as 1 048 576 words by 16 bits. The HYB 5116160BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5116160BSJ to be packaged in a standard SOJ 42 400 mil plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V ( 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type HYB 5116160BSJ-50 HYB 5116160BSJ-60 HYB 5116160BSJ-70 Pin Names A0 to A11 A0 to A7 RAS OE I/O1-I/O16 UCAS LCAS WE Row Address Inputs Column Addess Inputs Row Address Strobe Output Enable Data Input/Output Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Power Supply (+ 5 V) Ground (0 V) not connected Ordering Code on request on request on request Package Descriptions
P-SOJ-42-1 400 mil DRAM (access time 50 ns) P-SOJ-42-1 400 mil DRAM (access time 60 ns) P-SOJ-42-1 400 mil DRAM (access time 70 ns)
VCC VSS
N.C.
Semiconductor Group
2
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
P-SOJ-42 (400 mil) Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS A11 A10 A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 N.C. LCAS UCAS OE A9 A8 A7 A6 A5 A4 Vss
Pin Configuration Truth Table RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L WE H H H H H L L L H OE H H L L L H H H H I/O1-I/O8 High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z I/O9-I/O16 High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Operation Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write NOP
Semiconductor Group
3
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
I/O1 I/O2
I/O16
WE UCAS LCAS
. .
&
Data in Buffer
No. 2 Clock Generator 16
Data out Buffer
16
OE
8
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
12
Column Address Buffer(8)
8
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
16
Refresh Counter (12) 12 Row
256 x16
Address Buffers(12)
12
Decoder 4096
Row
Memory Array 4096x256x16
RAS
No. 1 Clock
Generator
Voltage Down Generator
VCC VCC (internal)
Block Diagram
Semiconductor Group
4
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,7.0) V Power supply voltage...................................................................................................-1.0V to 7.0 V Power dissipation..................................................................................................................... 1.0 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %, tT = 5 ns Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current,any input (0 V VIH Vcc + 0.3V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT Vcc + 0.3V) Average VCC supply current: -50 ns version -60 ns version -70 ns version (RAS, CAS, address cycling, tRC = tRC min.) Symbol Limit Values min. max. Vcc+0.5 0.8 - 0.4 10 10 2.4 - 0.5 2.4 - - 10 - 10 Unit Test Condition V V V V A A 1) 1) 1) 1) 1) 1)
VIH VIL VOH VOL II(L) IO(L) ICC1
- - -
100 90 80
mA mA mA
2) 3) 4) 2) 3) 4) 2) 3) 4)
Standby VCC supply current (RAS = CAS = VIH) ICC2
Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version (RAS cycling: CAS = VIH, tRC = tRC min.) Semiconductor Group 5
- - - -
2 100 90 80
mA mA mA mA
-
2) 4) 2) 4) 2) 4)
ICC3
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %, tT = 5 ns Parameter Symbol Limit Values min. max. 40 35 30 Unit Test Condition mA mA mA
2) 3) 4) 2) 3) 4) 2) 3) 4)
Average VCC supply current, during fast page mode: -50 ns version -60 ns version -70 ns version
(RAS = VIL, CAS, address cycling, tPC = tPC min.)
ICC4
- - -
Standby VCC supply current (RAS = CAS = VCC - 0.2 V)
Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version -70 ns version (RAS, CAS cycling, tRC = tRC min.)
ICC5 ICC6
-
1
mA
1)
- - -
100 90 80
mA mA mA
2) 4) 2) 4) 2) 4)
Average Self Refresh Current
(CBR cycle with tRAS>TRASSmin., CAS held low, WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
ICC7
_
1
mA
Capacitance TA = 0 to 70 C,VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A11) Input capacitance (RAS, UCAS, LCAS, WE, OE) I/O capacitance (I/O1-I/O16) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
6
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 -70 max. - - 10k 10k - - - - 50 35 - - - 50 64 max. min. - - 10k 10k - - - - 37 25 110 40 60 15 0 10 0 15 20 15 15 60 - 50 64 5 3 - max. min. - - 10k 10k - - - - 45 30 - - - 50 64 130 50 70 20 0 10 0 15 20 15 20 70 5 3 -
Unit Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 90 30 50 13 0 8 0 10 18 13 13 50 5 3 - ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7
Read Cycle
Access time from RAS Access time from CAS OE access time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tOEA tRCS tRCH tRRH tCLZ tOFF - - - - 25 0 0 0 0 0 50 13 25 13 - - - - - 13 - - - - 30 0 0 0 0 0 60 15 30 15 - - - - - 15 - - - - 35 0 0 0 0 0 70 20 35 20 - - - - - 20 ns ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Access time from column address tAA Column address to RAS lead time tRAL
Semiconductor Group
7
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 0 0 15 15 15 - - - 0 0 20 20 -70 max. 20 - - - max. min. 13 - - - max. min.
Unit Note
Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay
tOEZ tDZO tCDD tODD
0 0 13 13
ns ns ns ns
12 13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWP tWCS 8 8 0 13 13 0 10 0 - - - - - - - - 10 10 0 15 15 0 10 0 - - - - - - - - 10 10 0 20 20 0 15 0 - - - - - - - - ns ns ns ns ns ns ns ns 16 16 13 15
Write command to RAS lead time tRWL Write command to CAS lead time tCWL Data setup time Data hold time Data to CAS low delay tDS tDH tDZC
Read-Modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time OE command hold time tRWC tRWD tCWD tOEH 126 68 31 43 13 - - - - - 150 80 35 50 15 - - - - - 180 95 45 60 20 - - - - - ns ns ns ns ns 15 15 15
Column address to WE delay time tAWD
Fast Page Mode Cycle
Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCP tCPA tRAS tRHPC 35 10 - 50 30 - - 30 - 40 10 - 35 - - 35 - 45 10 - 40 - - 40 - ns ns ns ns 7
200k 60
200k 70
200k ns
Semiconductor Group
8
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
16F
Limit Values -50 min. -60 -70 max. - - max. min. - - 80 55 max. min. - - 95 65
Unit Note
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time CAS precharge to WE tPRWC tCPWD 71 48 ns ns
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time tCSR tCHR tRPC tWRP 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Write hold time referenced to RAS tWRH
CAS-before-RAS Counter Test Cycle
CAS precharge time tCPT 35 - 40 - 40 - ns
Self Refresh Cycle
RAS pulse width RAS precharge time CAS hold time tRASS tRPS tCHS 100k _ 95 -50 _ _ 100k _ 110 -50 _ _ 100k _ 130 -50 _ _ ns ns ns 17 17 17
Semiconductor Group
9
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 2 TTL loads and 100 pF. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)Either tDZC or tDZO must be satisfied. 14)Either tCDD or tODD must be satisfied. 15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh.
Semiconductor Group
10
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
UCAS LCAS
V
IH
VIL
tRAD tASR tASC tCAH
Column Address
tASR
Row Address
V
Address
IH
VIL
Row Address
tRCH tRAH tRCS tRRH tAA tOEA
WE
V IH VIL
V
OE
IH
VIL
tDZC tDZO tCAC tCLZ
Hi Z
tCDD tODD
I/O1-I/O16 IH (Inputs) V
IL
V
tOFF tOEZ
Valid Data Out Hi Z
V I/O1-I/O16 OH
(Outputs) V
OL
tRAC
"H" or "L"
Read Cycle
Semiconductor Group
11
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
UCAS LCAS
VIL
tRAD tASR tASC tCAH
Column Address
tASR
. Row Address
Address
V IH VIL
Row Address
tRAH
V
tWCS
tCWL t WP tWCH tRWL
WE
IH
VIL
OE
V IH VIL
tDS
I/O1-I/O16 IH (Inputs) V
IL V
tDH
Valid Data In
I/O1-I/O16 OH (Outputs) V
OL
V
Hi Z
"H" or "L"
Write Cycle (Early Write) Semiconductor Group 12
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
UCAS LCAS
VIL
tRAD tASR tASC tCAH
Column Address
tASR
. Row Address
V
Address
IH
VIL
Row Address
tRAH
V
WE
IH
tCWL tRWL tWP
VIL
tOEH
V
OE
IH
VIL
tODD tDZO tDZC tDS tOEZ
tDH
I/O1-I/O16 IH (Inputs) V
IL
V
Valid Data
tCLZ tOEA
Hi-Z Hi-Z
I/O1-I/O16 OH (Outputs) V
OL
V
"H" or "L"
Write Cycle (OE Controlled Write) Semiconductor Group 13
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRWC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tCRP
UCAS LCAS
V IH VIL
tRAH tASR
V
tCAH tASC
Column Address
tASR
Row Address
Address
IH
VIL
Row Address
tRAD
V IH
tAWD tCWD tRWD
tCWL tRWL tWP
WE
VIL
tAA tRCS
V IH
tOEA
tOEH
OE
VIL
tDZO tDZC
tDS tDH
Valid Data in
I/O1-I/O16 (Inputs) VIL
V IH
tCLZ tCAC
Data Out
tODD tOEZ
V I/O1-I/O16 OH
(Outputs) V OL
tRAC
"H" or "L"
Read-Write (Read-Modify-Write) Cycle Semiconductor Group 14
tRASP tRP tPRWC tCP tCAS tCAS tCAH tASC tASC
Column Address Column Address
V
RAS
IH
V IL
tCSH tRCD tCAS tRAL tASR
Row Address
tRSH tCRP
Semiconductor Group
UCAS LCAS
V
IH
V IL
tASR tASC
Column Address
tRAD tRAH tCAH tCAH
V
Address
IH
V IL
Row Address
Fast Page Mode Read-Modify-Write Cycle
V
tRCS tAWD tOEA tOEA tWP tWP tOEA tAWD tAWD
tRWD tCWD tCWL tCWL
tCPWD tCWD
tCPWD tCWD
tRWL tCWL
WE
IH
V IL
15
tAA
tWP
V
IH
OE
V IL
tCPA tDZC
Data In
tCPA tODD
Data In
V
IH
tDZC tCLZ tDZO tCLZ tCAC tRAC tOEZ tDH tDS
Data Out Data Out
tDZC tCLZ tOEH
tODD
Data In
I/O1-I/O16 (Inputs) V IL
tODD tCAC tAA
tOEH tOEZ tDS tDH
tOEH tAA tDS
Data Out
tDH
I/O1-I/O16 OH (Outputs) V
V
OL
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
"H" or "L"
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRASP
V IH
tRP
RAS
VIL
tRCD
UCAS LCAS
V IH
tPC tCP tCAS tCSH tCAS
tRHCP tRSH tCAS tCRP
VIL
tRAH tASR
Address
V IH VIL
Row Addr
tCAH
Column Address
tASC
tASC
tCAH tASC
tCAH tASR
Row Address Column Address
Column Address
tRAD tRCH tRCS tRCS tRCS
tRCH
V
IH
WE
VIL
V
tAA tOEA
IH
tCPA tAA tOEA
tCPA tAA tOEA tDZC tDZO tODD
tRRH
OE
VIL
tDZC tDZO tODD tCAC tOFF tCLZ tOFF tOEZ
Valid Data Out
tDZC tDZO
tCDD tODD
I/O1-I/O16 IH (Inputs) V
IL
V
tCAC tOFF tCLZ tOEZ
Valid Data Out
tCAC tCLZ
tOFF tOEZ
Valid Data Out
I/O1-I/O16 OH (Outputs) V
OL
V
"H" or "L"
Fast Page Mode Read Cycle Semiconductor Group 16
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRASP
V IH
tRP
RAS
VIL
tPC tCAS tRCD tCP
tCAS
tRSH tCAS tCRP
UCAS LCAS
V
IH
VIL
tRAL tRAH tASR tCAH tASC
Column Address
tASC tCAH
Column Address
V
tASC
tCAH
tASR
Column Address
Address
IH
VIL
Row Addr
Column Address
tRAD
V
tCWL tWCS tWCH tWP
tCWL tWCS tWCH tWP
tCWL tRWL tWCS tWCH tWP
WE
IH
VIL
V
OE
IH
VIL
tDH tDS
I/O1-I/O16 IH (Inputs) V
IL V Valid Data In
tDH tDS
Valid Data In
tDH tDS
Valid Data In
I/O1-I/O16 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
Fast Page Mode Early Write Cycle Semiconductor Group 17
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCRP tRPC
UCAS LCAS
V IH
VIL
tRAH tASR
tASR
Row Address
V
Address
IH
VIL
Row Address
I/O1-I/O16 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
RAS-Only Refresh Cycle
Semiconductor Group
18
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRC tRP
V
tRAS
tRP
RAS
IH
VIL
tRPC tCSR
UCAS LCAS
V IH VIL
tCRP tCHR tRPC
tCP tWRP tWRH
V
WE
IH
VIL
tOEZ
V
OE
IH
VIL
tCDD
I/O1-I/O16 IH (Inputs) V
IL V
tODD
I/O1-I/O16 OH (Outputs)VOL
V HI-Z
tOFF
"H" or "L"
CAS-Before-RAS Refresh Cycle Semiconductor Group 19
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRC
V
tRC tRP tRAS tRP
tRAS
IH
RAS
VIL
tRCD
UCAS LCAS
V
tRSH tCHR tCRP
IH
VIL
tRAD tRAH tASR tASC tWRP tCAH tWRH tASR
Row Address
V
Address
IH
VIL
Row Addr
Column Address
tRCS
V IH
tRRH
WE
VIL
tAA tOEA
V
OE
IH
VIL
tDZC tDZO
tCDD tODD
I/O1-I/O16 IH (Inputs) V
IL
V
tCAC tCLZ tRAC tOEZ
Valid Data Out
tOFF
I/O1-I/O16 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
Hidden Refresh Cycle (Read) Semiconductor Group 20
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRC tRP
V IH
tRC tRP tRAS
tRAS
RAS
VIL
tRCD
UCAS LCAS
V IH
tRSH
tCHR
tCRP
VIL
tRAD tRAH tASR tASC tCAH
Column Address
tASR
Row Address
V
Address
IH
VIL
Row Addr
tWCS
tWCH tWP
tWRP
tWRH
V
WE
IH
VIL
tDS
I/O1-I/O16 IH (Input) V IL
V
tDH
Valid Data
I/O1-I/O16 OH (Output) V OL
V
HI-Z
"H" or "L"
Hidden Refresh Cycle (Early Write) Semiconductor Group 21
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
tRP
RAS
V IH VIL
tRASS
tRPS
tRPC tCSR
V IH
tCHS
tCRP
tCP tWRP tWRH
UCAS LCAS
VIL
V
WE
IH
VIL
tOEZ
OE
V IH VIL
tCDD
I/O1-I/O16 IH (Inputs) V IL
V
tODD
I/O1-I/O16 OH (Outputs) V OL
V HI-Z
tOFF
"H" or "L"
CAS before RAS Self Refresh Cycle
Semiconductor Group
22
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
V
tRAS
IH
tRP tRSH tCAS tRAL tASR
Row Address
RAS
V
IL
tCSR
UCAS LCAS
V V IH IL
tCHR
tCPT
V
tASC
IH
tCAH tAA
Address
V
IL
Column Address
Read Cycle
WE
V V IH
tWRP tWRH
IL
tRCS
tCAC
tRRH tRCH
tOEA
V
OE
V
IH
IL
I/O1-I/O16 (Inputs)
V V
tDZC tDZO
tODD tCLZ tOEZ
Valid Data Out
tCDD tOFF
IH
IL
I/O1-I/O16 (Outputs)
V OH V OL
Write Cycle
V IH
tWRP tWRH
tWCS
tWCH
tRWL tCWL
WE
V V
IL IH
OE
V
IL
tDS
I/O1-I/O16 (Inputs) I/O1-I/O16 (Outputs)
V V IH IL IH IL IH HI-Z
tDH
Valid Data In
V V
Read-Modify-Write Cycle
V
tWRP
tWRH
tRCS tAA
tAWD tCWD tCAC tOEA tDS
tCWL tRWL tWP tOEH
WE
V
IL
V
OE
IH
V
IL
I/O1-I/O16 (Inputs)
V V
tDZC tDZO
IH
tDH
Data In
IL
I/O1-I/O16 (Outputs)
V OH V OL HI-Z
tCLZ
tCAC
D.Out
tODD tOEZ
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 23
HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM
Package Outlines
Plastic Package P-SOJ-42 (400 mil) (Small Outline J-lead, SMD)
1)
10.3
-0.3
B
1.27 0.43
0.81 max. 9.4 0.18 A 42x 0.08 11.2
+ 0.1 -
+ - 0.25
+ 0.15 -
0.18
B
25.4
42
22
GPJ05853
1
1)
21
27.43
-0.25
A
Index marking
1) does not include plastic or metal protusion of 0.15 max per side
Semiconductor Group
24

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